Digital ASIC Designer

Category:

Engineering

Employment Type:

Contract

Reference:

BH-379579

Digital ASIC Designer

Scope:

* Set up full digital RTL to GDS flow from scratch - Standard IP cells provided.
* Produce tape out-ready digital blocks from design specifications.
* Integrate custom Gbps speed IO cells in digital place and route.
* Integrate custom clock and data routing in analog top-level assembly - Distribute clock and data in large-scale analog top-level assembly.
* Verify design and integration over manufacturing corners and timing corners.

Expertise with the following tools is required:

* Cadence Genus.
* Cadence Innovus.
* Cadence Tempus.
* Cadence Liberate.

Pluses:

* Version control tools such as Git
* Scripting language such as TCL, Python or Perl.

Estimated Min Rate: $70.00
Estimated Max Rate: $90.00

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit https://www.yoh.com/applicants-with-disabilities

to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.