Senior Engineer, Design Verification

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Work on verification of Marvell's AI/ML, Network processing, Compute, Automotive, and Baseband SoCs and IPs. Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers. Develop System Verilog (SV) test-benches based on UVM to instantiate the entire design and integrate verification components from block and subsystem environments. Develop SV-UVM based test bench components like drivers, monitors, scoreboards, agents for use in block/subsystem/fullchip test benches. Develop functional coverage components such as SV assertions and coverage bins. Develop verification test plans and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete. Develop tests and tune the environment to achieve coverage goals. Debug failures and work with designers to resolve issues. Use simulation tools to debug failures by reviewing waveforms and trace the source of the issue. Work with design and architecture teams to isolate issues, file bug reports and verify correct functionality with the fix provided. Architect, develop and maintain tools to streamline the design of state-of-the-art multicore SoCs. Develop scripts to improve test writing timelines, scripts to aid simulation debug, and flows to improve overall productivity to ensure verification timelines are met. Analysis/closure of code and functional coverage. Wage $120,000.00 - $135,000.00 per year. Telecommuting is permitted.

What We're Looking For

Master's or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Must have work/internship experience or completed graduate coursework/research in each of the following:

* Verilog/System Verilog development.
* Python, Perl, UVM methodology.
* Semiconductor Design Verification techniques including assertions, constraints, coverage, modeling, and interfaces.
* Programming including object-oriented programming including C, C++, SystemC.
* Advanced Hardware Design Functional Verification.
* Digital Logic Design including Verilog RTL Design.
* Computer Architecture, Processors and Caches such as ARM microprocessor architectures, MESI cache protocol.
* FPGA development flow.
* EDA tools.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.