Principal Engineer, Digital IC Design

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Own a significant portion of switch design. Work on RTL design of Queuing, Scheduling, QoS or Buffer management. Perform microarchitecture, RTL design and backend closure of block working closely with Architecture, DV and PD teams. Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery. Code and deliver high-quality RTL to the PD and DV teams. Collaborate with the Architecture team to define new features and suggest optimizations for power, latency, and performance. Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations. Wage $180,000.00 - $195,000.00. Telecommuting is permitted within normal commute distance of office location.

What We're Looking For

Master's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and three (3) years of experience in the job offered or related occupation.

Experience must include three (3) years with each of the following:

* Working with various interface protocols and Common RTL design practice or micro-architecture and logic design in IO subsystem for ARM Server processors.
* Using Verilog System Verilog, PERL, and TCL.
* Clock domain crossing techniques, low power design, Synopsys Suite (DC, VCS, PrimeTime, Formality).
* Participating in various asynchronous FIFOs, Physical design and placement and routing.
* Designing of DMA engines to improve performance.
* Design IO interface logic RTL using common protocols: I2C, AXI, DMA.
* Coding using Verilog/System Verilog for RTL and scripting (PERL, TCL).

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.