New

Architect DSP

Marvell Semiconductor, Inc.
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Feb 03, 2026
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Group Description Marvell's Architecture team leads the industry in wireline Ethernet communication technologies, delivering solutions for applications ranging from hyperscale data center interconnects to industrial PHYs. Their portfolio spans speeds up to 1.6 Tb/s and supports diverse media types, including optical fibers, high-speed coaxial cables, and shielded/unshielded twisted pair cables. The underlying core technologies that enable these products are state of the art of equalization techniques like Maximum likelihood sequence estimation, timing synchronization, cross talk and echo cancellation techniques, error control coding techniques such as LDPC, product and concatenated codes, combined with architectural and circuit innovations to enable low power high speed implementation of these complex algorithms. Come join Marvell to work on the DSP and architecture challenges that need to be solved to enable products and technologies that will determine the future direction for the entire industry. What You Can Expect Lead to design and simulate DSP architecture, define key capabilities, performance requirements and drive specifications for both analog and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research activities in digital signal processing for Base-T, SerDes and optical channels Lead designers to ensure circuit architecture can be efficiently implemented. Lead to Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers. Provide guidance on test plans for lab characterization once design comes back from fab. Lead in chip lab bring up. What We're Looking For Ph.D., or M.S. in Electrical Engineering, Computer Science or related fields and 12+ years of related design experience. Strong knowledge of communications theory and system design, and digital signal processing. Deep architectural understanding of: High-speed interconnects and Ethernet protocols High Speed SerDes and Ethernet PHY architecture Proven hands-on experience with performance modeling, simulation, and architectural trade-off analysis. Proficiency in C/C++, Python, and modeling environments. Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR) or FEC (RS, soft decoding, Viterbi algorithm) Experience with ADC-based wireline transceivers and/or coherent DSP architectures is a plus. Leadership & Influence Strong conceptual thinking and architectural innovation capabilities. Collaborative leadership style; ability to work across silicon, systems, software, and customer engineering teams. Exceptional communication skills; able to convey complex architectural concepts to technical and executive audiences. Demonstrated experience mentoring and influencing engineering talent and product direction. Expected Base Pay Range (USD) 220,280 - 330,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MM1